Synthesisable FSM
Deliverable: A finite state machine written in VHDL, synthesised, with the inferred hardware inspected in the schematic viewer and confirmed to match the intended design.
Course
VLSI and VHDL
Hardware description taught as hardware, not as programming — RTL that synthesises, testbenches that prove it, and designs that meet timing on a real FPGA.
- Duration: 5 months
- Classroom
- Level: advanced
What you will be able to do
- Write synthesisable RTL in VHDL and Verilog
- Think in concurrent hardware rather than sequential statements
- Build finite state machines that synthesise predictably
- Write testbenches that prove a design rather than demonstrate it
- Read a timing report and fix a setup violation
- Implement a design on an FPGA and verify it on hardware
Who this course is for
- Electronics and communication engineering graduates and final-year students
- Engineers moving into digital design or verification
- Comfortable with digital electronics and logic design
- Some programming experience in any language
Syllabus
7 modules · 5 months
Module 1. Digital design refresher
- Combinational and sequential logic
- Flip-flops, setup and hold
- Metastability and synchronisers
- Clock domains and why crossing them is dangerous
Module 2. VHDL fundamentals
- Entities, architectures and signals
- Concurrent versus sequential statements
- Processes, sensitivity lists and common traps
- Writing for synthesis rather than for simulation
Module 3. Verilog
- Modules, nets and registers
- Blocking and non-blocking assignment, and when each is correct
- Always blocks and inferring the intended hardware
- Comparing the same design in both languages
Module 4. RTL design
- Finite state machines and encoding
- Counters, shift registers and arithmetic blocks
- Memory inference — block RAM and distributed
- Pipelining and throughput
Module 5. Verification
- Testbench structure and stimulus generation
- Self-checking testbenches and assertions
- Corner cases, and why directed tests miss them
- Coverage as a measure of what you have actually tested
Module 6. Synthesis and timing
- Synthesis, mapping and what the tool inferred
- Constraints and clock definition
- Reading a timing report
- Fixing a setup violation without breaking function
Module 7. FPGA implementation
- Place and route, and resource utilisation
- Pin constraints and board bring-up
- On-chip debugging with an integrated logic analyser
- Verifying behaviour on hardware against simulation
Tools and technologies you will use
- VHDL and Verilog
- Xilinx Vivado or Intel Quartus
- ModelSim or the built-in simulator
- FPGA development boards
- Logic analyser
Projects you will build
Self-checking testbench
Deliverable: A testbench that automatically reports pass or fail across a stimulus set including corner cases, catching a deliberately introduced bug without a human reading waveforms.
Timing closure
Deliverable: A design that initially fails timing, analysed from the timing report and fixed by pipelining or restructuring, with the slack before and after recorded.
Working FPGA implementation
Deliverable: A complete design implemented on an FPGA board, verified on hardware with an on-chip logic analyser, and shown to behave as the simulation predicted.
Where this course can take you
- RTL Design Engineer
- Verification Engineer
- FPGA Engineer
- Physical Design Engineer
- Hardware Engineer
Duration, modes and fees
- Duration
- 5 months
- Delivery modes
- Classroom
- Fees
- Share your details for the current fee
- Fees vary by batch. FPGA boards, tool licences and lab time are included. Classroom mode only.
Placement assistance
Every student gets placement assistance — that is what 100% placement assistance means. It is support for all, not a job for all. We do not promise a specific salary, a specific number of interviews, or placement at any named company, and you should be wary of anyone who does.
What is included
- A place in the monthly placement drive, held every third Saturday
- The readiness programme every second Saturday — mock interviews and preparation
- CV review against the specific roles you are targeting
- Portfolio review, so your project work is presented the way a reviewer will read it
- Access to the vacancy pool employers send directly to the Samyak network
- Guidance on which roles realistically fit your background and which do not
- A place in the next drive, with coaching, if you are not selected in this one
What is not included
- Any guarantee of a job, an interview, or a particular salary
- Placement at a named or partner company
- Applying to jobs on your behalf
- Support before you have completed the course and its project work
- Visa, relocation or overseas placement assistance
It is not code, it is a circuit
The single biggest obstacle is that VHDL and Verilog look like programming languages.
They are not. Everything in an architecture happens simultaneously. A signal assignment is a wire, not a store. Two processes driving the same signal is a short circuit, not a race condition to be reasoned about. Beginners who carry sequential thinking across write code that simulates and synthesises into something else entirely.
The second module exists to break that, and everything afterwards is easier once it is broken.
Look at what the tool inferred
Writing RTL and never opening the schematic viewer is how people produce accidental latches for years.
The first project requires inspecting the synthesised hardware and confirming it matches what you intended. Frequently it does not, and the gap between what you wrote and what the tool built is where real understanding starts.
A testbench that needs you to watch it is not a testbench
Reading waveforms proves a design works for the case you happened to look at.
Self-checking testbenches report pass or fail on their own, which means they can be rerun on every change without anybody’s attention. The verification project plants a bug and requires your testbench to catch it unassisted — because verification hires in larger numbers than design, and this is the skill it tests.
Simulation is not hardware
A design that simulates perfectly can fail on the board — timing, a synthesis mismatch, a clock domain crossing nobody synchronised.
That is why the last project has to run on an FPGA and be verified with an on-chip analyser. The distance between “it works in the simulator” and “it works” is where a lot of engineering careers are made.
Questions
VLSI and VHDL — frequently asked questions
Is VHDL a programming language?
No, and treating it as one is the reason most beginners struggle. It describes hardware that exists all at once, not instructions that execute in order. A process is not a function and a signal is not a variable. The second module spends real time on this because everything afterwards depends on making the mental switch.
VHDL or Verilog?
Both are taught, because Indian VLSI employers are split — Verilog and SystemVerilog dominate verification, VHDL remains common in defence, aerospace and European-influenced firms. Learning the same design in both is not repetition; it makes the underlying hardware thinking clearer.
Do I need an FPGA board of my own?
No, boards are provided and the course is classroom-only for that reason. Hardware verification matters because a design that simulates perfectly can still fail on silicon through timing or a synthesis mismatch, and finding that gap is a large part of the education.
Is there work in VLSI in India?
Yes, and it is one of the stronger engineering markets — design centres in Bengaluru, Hyderabad, Noida and Pune hire RTL and verification engineers steadily. Verification hires in larger numbers than design. It is competitive and expects a solid digital electronics foundation, which is why that is a real prerequisite here.
Enquire about VLSI and VHDL
Three details is all we need. A course advisor will call you back.
Related courses
- Embedded Systems
Firmware written close to the metal — registers, interrupts, timers and buses — debugged on real hardware, because embedded bugs live where a simulator cannot show them.
- PCB Design
Board design taken to manufacture — schematic, footprints, layout, planes and Gerbers — with the checks that decide whether a fab house builds it or sends it back.
- MATLAB and Simulink
MATLAB taught as an engineering tool — vectorised computation, signals, control and Simulink — with the habit of checking a simulation against something you already know.
- IoT (Internet of Things)
Connected hardware from sensor to dashboard — microcontrollers, wireless protocols, cloud ingestion and the power and reliability problems that decide whether a device survives deployment.
Next step
Talk to a course advisor
Tell us what you want to learn and we will help you pick the right course, batch and mode.